SPARK-6, Spartan-6 FPGA Development Board User Constraint File. NET “CLK” LOC = P126; TIMESPEC TS_CLK = PERIOD “CLK” 100 MHz HIGH 50%; NET “LED[0]” LOC = P119; NET “LED[1]” LOC = P118; NET “LED[2]” LOC = P117; NET “LED[3]” LOC = P116; NET “LED[4]” LOC = P115;. NET “LED[5]” LOC = P114; NET “LED[6]” LOC