# User Constraint File for SPARK-3, Spartan3 FPGA Development Board v 1.0 # Remove or comment out lines correspond to unused pins. # Clock input NET “CLK” LOC = P40; NET “CLK” TNM_NET = CLK; TIMESPEC TS_CLK = PERIOD “CLK” 12 MHz HIGH 50%; # Onboard LEDs NET “LED[0]” LOC = P3; NET “LED[1]” LOC